Channel allocation apparatus of OSU in WDM system

ABSTRACT

A channel allocation apparatus of an OSU in a WDM system includes: an optical signal converter for performing a conversion operation between an E 1  data frame and an optical signal; a channel allocating unit for performing a counting operation by a certain unit on the E 1  data, detecting an channel allocated to the E 1  data or allocating a channel to the E 1  data; an E 1  framer for reframing the E 1  data frame outputted from the optical signal converter to output it to the channel allocating unit, and framing the E 1  data outputted from the channel allocating unit to output it to the optical signal converter; and a microprocessor for controlling an operation of the E 1  framer. After the E 1  data is counted by a certain unit to sequentially identify a plurality of channels, a channel data is assigned to a corresponding channel or a channel data assigned to the channel is detected.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a wavelength divisionmultiplexing (WDM) system, and more particularly, to a channelallocation apparatus of an optical supervisory channel unit (OSU) in theWDM system.

[0003] 2. Description of the Background Art

[0004]FIG. 1 is a schematic view of the WDM system.

[0005] As shown in FIG. 1, a multiplexer 10 multiplexes a plurality ofoptical signals each having a different wavelength (λ1, . . . , λn), andan optical amplifier 12 amplifies the multiplexed optical signal to acertain level.

[0006] An optical supervisory channel unit (OSU) 14 outputs an opticalsignal which has assigned a data channel and a voice channel requiredfor managing a network.

[0007] An optical coupler 16 couples the optical signals of the opticalamplifier 12 and of the OSU 14 and transmits the coupled signal to adestination. These 20 elements constitute an optical transmitting unit.

[0008] In general, the OSU provides a data communication and anorderwire (OW) channel between a WDM system-based systems such as a WDMterminal, a repeater or an optical add-drop multiplexer (OADM), and isroughly classified into a structure using an STM-1 (155.520 Mbps) and astructure using an E1 (2.048 Mbps).

[0009]FIG. 2 shows an example of a conventional OSU 100 using the STM-1.

[0010] As shown in FIG. 2, the OSU 100 includes an optical signalconverter 20, an STM-1 framer 22, an FPGA (Field Programmable GateArray) 24, a backboard connector 26 and a microprocessor 28.

[0011] The optical signal converter 20 performs a conversion operationbetween a STM-1 frame data and an optical signal. The STM-1 framer 22,implemented as an application specific IC (ASIC), allocates/extracts adata communication channel data (DCCD) and an orderwire data (OWD)to/from an overhead of the STM-1 frame data as well as framing/reframingthe STM-1.

[0012] The FPGA 24 temporarily stores a DCCD, an OWD, a DCC clock signal(DCCCK), an OW clock signal (OWCK) and a frame pulse (OWFP), and thebackboard connector 26 connects an external data processing unit (notshown) and the OSU 100.

[0013] As shown in FIG. 3, the STM-1 framer 22 consists of a framer 121forming an STM-1 frame, an overhead inserting unit 122 for inserting anoutputted DCCD and OWD outputted from the FPGA 24 into the overhead ofthe formed STM-1 frame, an overhead detecting unit 123 for extractingthe STM-1 frame, the DCCD and the OWD from the received STM-1 framedata, and a reframer 124 for reframing the STM-1 frame extracted fromthe overhead detecting unit 123.

[0014] The operation of the OSU 100 using the conventional STM-1 frameconstructed as described above will now be explained.

[0015] First, the DCCD, OWD, clock signals (DCCCK, OWCK) and the OWFPinputted from an external data processing unit (not shown0 through thebackboard connector 26 is stored in the FPGA 24.

[0016] After forming the STM-1 frame, the STM-1 framer 22 inserts theDCCD and the OWD into the overhead of the STM-1 frame under the controlof the microprocessor.

[0017] That is, as shown in FIG. 3, the framer 121 of the STM-1 framer22 forms an STM frame, and the overhead inserting unit 122 inserts theDCCD and the OWD outputted from the FPGA 24 into the overhead of theSTM-1 frame under the control of the microprocessor 28.

[0018] Then, the optical signal converter 20 converts the STM-1 framedata outputted from the overhead inverting unit 122 into an opticalsignal by using a 155 M laser diode (not shown) and outputs the opticalsignal to the WDM system.

[0019] Meanwhile, the optical signal transmitted from the WDM system isconverted into an STM-1 frame data by the optical signal converter 20,and the overhead detecting unit 123 of the STM-1 framer 22 detects anoverhead of the STM-1 frame data under the control of the microprocessor28 and outputs the DCCD, the OWD, the clock signal and the OWFP to theFPGA 24, and the STM-1 frame to the reframer 124.

[0020] Accordingly, the DCCD, the OWD, the clock signal and the OWFPinputted to the FPGA 24 are outputted to the external data processingunit (not shown) through the backboard connector 26, and the reframer124 reframes the inputted STM-1 frame.

[0021] The OSU using the STM-1 implements the STM-1 framer whichframes/reframes the STM-1 signal and extracts/inserts the DCCD and theOWD as the ASIC and interworks with the external data processing unitthrough the FPGA and the backboard connector.

[0022]FIG. 4 is a conventional OSU 200 using an E1.

[0023] As shown in FIG. 4, the conventional OSU 200 using the E1consists an optical signal converter 30, an E1 framer 32, a time slotinterface (TSI) 34, a backboard connector 36 and a microprocessor 38.

[0024] The E1 framer 32 frames an El frame data to a time slot dataunder the control of the microprocessor 38, and the TSI 34 interfacesthe time slot data of the E1 framer 32 in a time division multiplexing(TDM) method according to a control signal outputted from themicroprocessor 38 and extracts a DCCD and an OWD.

[0025] In addition, the TSI 34 interfaces the DCCD and the OWD inputtedfrom an external data processing unit (not shown) through the backboardconnector 36 by the TDM method to input them into the time slot data,and outputs them to the E1 framer 32.

[0026] In this manner, when the E1 framer 32 and the TSI 34 are used,the E1 framer 32 performs an E1 framing/reframing and the TSI 34separates a channel, and forms corresponding channels as a serial dataaccording to a use and transmits them to the backboard connector 36.

[0027] However, the conventional OSU using the STM-1 uses the STM-1framer chip and the 155M laser diode for a low rate data, a cost chargeis increased. Especially, since the STM-1 framer interworks with themicroprocessor, much time is taken for the performance implementation,the board testing, and the like.

[0028] In addition, in the OSU using the E1, the commercial chips thatgenerally handle the DS-1E such as the TSI follows a coding method suchas an AMI and an HDB3. Accordingly, the commercial chip such as the TSIis not suitable to be used for an optical communication system on thebasis of a Manchester code and an NRZ signal in a physical layer, andespecially, for the low rate data.

[0029] This is resulted from unnecessary functions as well as from adifference in the interface method. If the OSU using the conventional E1is implemented by using the commercial chip, much time is taken forimplementing a function, and operating chips such as a processor arerequired to designate an address.

[0030] The above references are incorporated by reference herein whereappropriate for appropriate teachings of additional or alternativedetails, features and/or technical background.

SUMMARY OF THE INVENTION

[0031] Therefore, an object of the present invention is to provide achannel allocation apparatus of an OSU that is capable of allocating anddetecting a channel flexibly in a WDM system which operates a networkusing a low rate such as an E1 class.

[0032] Another object of the present invention is to provide a channelallocation apparatus of an OSU that is capable of simplifying a functionimplementation and being implemented as one chip.

[0033] To achieve at least the above objects in whole or in parts, thereis provided a channel allocation apparatus of an OSU in a WDM systemincluding: an optical signal converter for performing a conversionoperation between an E1 data frame and an optical signal; a channelallocating unit for performing a counting operation by a certain unit onthe E1 data, detecting an channel allocated to the E1 data or allocatinga channel to the E1 data; an E1 framer for reframing the E1 data frameoutputted from the optical signal converter to output it to the channelallocating unit, and framing the E1 data outputted from the channelallocating unit to output it to the optical signal converter; and amicroprocessor for controlling an operation of the E1 framer.

[0034] To achieve at least these advantages in whole or in parts, thereis further provided a channel allocation apparatus of an OSU in a WDMsystem including: an optical signal converter for performing aconversion operation between an E1 data frame and an optical signal; ademultiplexing unit for counting the E1 data by 8 bit unit, counting itto separate a plurality of channels and detecting a data allocated tothe separated channels; a multiplexing unit for counting the E1 data by8 bit unit to separate it to a plurality of channels, allocating acertain data to the separated channel and forming an E1 data; an E1framer for reframing the E1 data frame outputted from the optical signalconverter to output it to the demultiplexing unit, framing the E1 dataoutputted from the multiplexing unit to output it to the optical signalconverter; and a microprocessor for controlling an operation of the E1framer.

[0035] Additional advantages, objects, and features of the inventionwill be set forth in part in the description which follows and in partwill become apparent to those having ordinary skill in the art uponexamination of the following or may be learned from practice of theinvention. The objects and advantages of the invention may be realizedand attained as particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The invention will be described in detail with reference to thefollowing drawings in which like reference numerals refer to likeelements wherein:

[0037]FIG. 1 is a schematic view of a general WDM system;

[0038]FIG. 2 is a view showing one example of an OSU using an STM-1 ofFIG. 1;

[0039]FIG. 3 is a detailed view illustrating the STM-1 framer of FIG. 2;

[0040]FIG. 4 is a view illustrating one example of an OSU using the E1of FIG. 1;

[0041]FIG. 5 is a block diagram of a channel allocation apparatus of theOSU in a WDM system in accordance with the present invention;

[0042]FIG. 6 is a detail view illustrating a demultiplexing unitprovided in the channel allocation apparatus of FIG. 5;

[0043]FIG. 7 is a detailed view illustrating a multiplexing unitprovided in the channel allocation apparatus of FIG. 5; and

[0044]FIG. 8 is a view showing an example of a channel allocation of anE1 data.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045]FIG. 5 is a block diagram of a channel allocation apparatus of theOSU in a WDM system in accordance with the present invention.

[0046] As shown in FIG. 5, the OSU of the present invention includes anoptical signal converter 40, an El framer 42, a channel allocation unit44, a backboard connector 46 and a microprocessor 48.

[0047] The channel allocation unit 44 extracts a DCC data (DCCD), an OWdata (OWD), clock signals (DCCCK, OWCK) and a frame pulse (OWFP) fromthe E1 data outputted from the E1 framer 42, and allocates the DCCD, theOWD, the clock signal and the OWFP outputted from the backboardconnector 46 to the E1 data.

[0048]FIGS. 6 and 7 are view illustrating detailed constructions of ademultiplexing unit 400 and a multiplexer (500) of the channelallocation unit 44.

[0049] As shown in FIG. 6, the demultiplexing unit 400 includes a timingunit 410 for dividing a reference clock and outputting a DCC clocksignal (DCCCK), an OW clock signal (OWCK) and a 2.048 MHz clock signal;a counter unit 420 for counting the clock signal (2.048 MHz) accordingto a frame start (FS) signal and outputting a count value of 0˜255; anenabling unit 430 for generating an enable signal in each channel of theE1 frame according to a count value of the counter unit 420; ademultiplexer 440 activated by an enable signal outputted from theenabling unit 430, demultiplexing the El data according to the framestart signal (FS) and detecting an DCCD and an OWD; a buffer unit 450for storing the DCCD and the OWD detected by the demultiplexer 440; aDCC multiplexer 460 and an OW multiplexer 470 each activated by anenable signal outputted from the enabling unit 430, multiplexing theDCCD and the OWD stored in the buffer unit 450, and outputting areceiving DCC data (RXDCCD), a receiving OW data (RXOWD), a receivingclock signal (RXDCCCK, RXOWCK) and a receiving frame pulse (RXOWFP).

[0050] As shown in FIG. 7, the multiplexing unit 500 is constructedsymmetrical to the demultiplexing unit 400, detailed descriptions ofwhich are omitted.

[0051] The operation of the OSU of the system in accordance with thepresent invention constructed as described above will now be explainedwith reference to the accompanying drawings.

[0052] The optical signal transmitted from the WDM system is convertedinto an E1 frame in the optical signal converter 40, and the E1 framer42 reframes the E1 frame under the control of the microprocessor 48 andoutputs the E1 data to the channel allocation unit 44.

[0053] The channel allocation unit 44 performs a 8-bit unit countingoperation on the E1 data to detect the channel data (DCCD and OWD)allocated to each channel and outputs the channel together with theclock signals (DCCCK and OWCK) and the frame pulse (OWFP) to thebackboard connector 46.

[0054] That is, as shown in FIG. 8, the E1 data includes a total 32channels (time slots) by taking 8 bit as one channel, and a data regionis assigned to 30 channels except for ‘0’ and ‘16’.

[0055] Accordingly, the DCC data region is assigned by using theconsecutive DCC data channel. For example, N-DCC1-N-DCC4 are assigned toDCC1, NDCC5˜N-DCC8 to DCC2, and N-DCC9˜N-DCC12 to DCC3.

[0056] Since the OW data channel is discontinuous, each channel isassigned as the OW data region. In this respect, the DCC data rate is a768 Kbps, and the OW data rate is a 192 Kbps.

[0057] The timing unit 410 divides the reference clock and outputs theDCCCK, the OWCK and the 2.048 MHz clock signal, and the counter unit 420counts the entire channels of the E1 frame. At this time, the counter420 counts the clock signal (2.048 MHz) according to the frame startsignal (FS) and outputs count values of 0˜255.

[0058] The enabling unit 430 receives the count value and generates ahigh level enable signal when the count value corresponding to achannel-allocated bit is inputted. and the demultiplexer 440 isactivated by the enable signal, demultiplexes the inputted E1 data anddetects a channel data allocated to each channel.

[0059] In other words, the demultiplexer 440 is operated by the highlevel enable signal, extracts the DCCD and the OWD from the E1 datainputted with the start of the FS signal and outputs them to the bufferunit 450. At this time, the buffer unit 450, a device for conforming thedata rate, includes three buffers (DCC1˜DCC3) for storing the DCC dataand the buffers (OW1˜OW3) for storing the OW data.

[0060] Accordingly, the DCC multiplexer 460 and the OW multiplexer 470are operated by the enable signal outputted from the enabling unit 430and multiplex the DCCD stored in the buffer 450 according to the DCCCKand the OWCK outputted from the timing unit 410.

[0061] That is, since the enable unit 430 outputs the high level enablesignal when the channel-allocated bit is inputted, at the time when eachbuffer (DCC1˜DCC3 and OW1˜OW3) of the buffer unit 450 is filled, the DCCmultiplexer 460 multiplexes the DCCD stored in the buffer 450 accordingto the DCCCK and outputs the receiving DCC data (RXCDDC) and thereceiving clock signal (RXCDDDK), and the OW multiplexer 470 multiplexesthe OWD stored I the buffer 450 according to the OWCK and outputs thereceiving OW data (RXOWD), the receiving clock signal (RXOWCK) and thereceiving clock signal (RXOWFP) to the backboard connector 46.

[0062] Meanwhile, the channel allocation unit 44 performs a 8-bit unitcounting operation on the E1 data to allocate the channel data (DCCD andOWD) to each channel and output it to the E1 framer 42, and the E1framer 42 frames the E1 data outputted from the channel allocation unit44 and outputs the E1 frame to the optical signal converter 40 under thecontrol of the microprocessor 48. Then, the optical signal converter 40optical-signal converts the E1 frame outputted from the E1 framer 42 andoutputs it to the WDM system.

[0063] That is, as shown in FIG. 7, the timing unit 510 divides thereference clock and outputs the DCCCK, the OWCK and the 2.048 MHz clocksignal, and the counter unit 520 counts the clock signal (2.048 MHz)according to the frame start signal (FS) and outputs a count value of0˜255.

[0064] The enabling unit 530 receives the count value and generates ahigh level enable signal when the count value of the bit to which achannel is to be allocated, is inputted.

[0065] At this time, the DCC demultiplexer 560 and the DCC clock(TXDCCK) are transmitted to the backboard connector 46 to read atransmitting DCC data (TXDCCD), and the OW demultiplexer 570 transmits atransmitting OW clock (TXOWCK) to the backboard connector 46 to read atransmitting OW data (TXOWD) by taking a transmitting frame pulse(TXOWFP) as a start signal.

[0066] When the data is read, the DCC demultiplexer 560 and the OWdemultiplexer 570 respectively output the TXDCCD and TXOWD to the bufferunit 55 according to the enable signal, and the mutliplexer 540multiplexes the DCC data (DCC1˜DCC3) and the OW data (OW1˜OW3) stored inthe buffer unit 55 whenever the enable signal becomes a high level, toform the E1 data and outputs the E1 data together with the 2.048transmitting clock (TX CLOCK).

[0067] As so far described, the channel allocation apparatus of an OSUin a WDM system of the present invention has the following advantages.

[0068] That is, for example, since the DCC data and the OW data areallocated to and extracted from the E1 frame by using a simple block,the channel can be flexibly allocated and detected in the WDM systemwhich operates a network using a low rate such as the E1 class.

[0069] In addition, a development term of the OSU can be shortened bysimplifying the channel allocation block, and especially, the functionsuitable to a system is easily implemented and a fabrication cost can bereduced.

[0070] The foregoing embodiments and advantages are merely exemplary andare not to be construed as limiting the present invention. The presentteaching can be readily applied to other types of apparatuses. Thedescription of the present invention is intended to be illustrative, andnot to limit the scope of the claims. Many alternatives, modifications,and variations will be apparent to those skilled in the art. In theclaims, means-plus-function clauses are intended to cover the structuredescribed herein as performing the recited function and not onlystructural equivalents but also equivalent structures.

What is claimed is:
 1. A channel allocation apparatus of an OSU in a WDMsystem comprising: an optical signal converter for performing aconversion operation between an E1 data frame and an optical signal; achannel allocating unit for performing a counting operation by a certainunit on the E1 data, detecting an channel allocated to the E1 data orallocating a channel to the E1 data; an E1 framer for reframing the E1data frame outputted from the optical signal converter to output it tothe channel allocating unit, and framing the E1 data outputted from thechannel allocating unit to output it to the optical signal converter;and a microprocessor for controlling an operation of the E1 framer. 2.The apparatus of claim 1, wherein the certain unit is an 8 bit.
 3. Theapparatus of claim 1, wherein the channel allocation unit comprises: ademultiplexing unit for counting the E1 data by 8 bit unit to separate aplurality of channels and detecting a data assigned to the separatedchannel; and a multiplexing unit for counting the E1 data by 8 bit unitto separate a plurality of channels and assigning a certain data to theseparated channel to form an E1 data.
 4. The apparatus of claim 3,wherein the demultiplexing unit comprises: a counter unit for countingthe entire channels of the E1 frame; an enabling unit for generating anenable signal in each channel according to the count value; ademultiplexer activated by the enable signal, demultiplexing theinputted E1 data and detecting the channel assigned to each channel; abuffer unit for storing the detected channel data; and a channel datamultiplexer activated by the enable signal, multiplexing the channeldata stored in the buffer unit and outputting the multiplexed channeldata to an external data processing unit.
 5. The apparatus of claim 4,wherein the channel data is a data communication channel (DCC) data andan orderwire (OW) data.
 6. The apparatus of claim 3, wherein themultiplexing unit comprises: a counter unit for counting the entirechannels of the E1 frame; an enabling unit for generating an enablesignal in each channel according to the count value; a channel datademultiplexer activated by the enable signal and demultiplexing achannel data; a buffer unit for storing the demultiplexed channel data;and a multiplexer activated by the enable signal, multiplexing thechannel data stored in the buffer unit and assigning the channel data tothe E1 data.
 7. The apparatus of claim 6, wherein the channel data is adata communication channel (DCC) data and an orderwire (OW) data.
 8. Achannel allocation apparatus of an OSU in a WDM system comprising: anoptical signal converter for performing a conversion operation betweenan E1 data frame and an optical signal; a demultiplexing unit forcounting the E1 data by 8 bit unit, counting it to separate a pluralityof channels and detecting a data allocated to the separated channels; amultiplexing unit for counting the E1 data by 8 bit unit to separate itto a plurality of channels, allocating a certain data to the separatedchannel and forming an E1 data; an E1 framer for reframing the E1 dataframe outputted from the optical signal converter to output it to thedemultiplexing unit, framing the E1 data outputted from the multiplexingunit to output it to the optical signal converter; and a microprocessorfor controlling an operation of the E1 framer.
 9. The apparatus of claim8, wherein the demultiplexing unit comprises: a counter unit forcounting the entire channels of the E1 frame; an enabling unit forgenerating an enable signal in each channel according to the countvalue; a demultiplexer activated by the enable signal, demultiplexingthe inputted E1 data and detecting the channel assigned to each channel;a buffer unit for storing the detected channel data; and a channel datamultiplexer activated by the enable signal, multiplexing the channeldata stored in the buffer unit and outputting the channel to an externaldata processing unit.
 10. The apparatus of claim 9, wherein the channeldata is a data communication channel (DCC) data and an orderwire (OW)data.
 11. The apparatus of claim 8, wherein the multiplexing unitcomprises: a counter unit for counting the entire channels of the E1frame; an enabling unit for generating an enable signal in each channelaccording to the count value; a channel data demultiplexer activated bythe enable signal and demultiplexing a channel data; a buffer unit forstoring the demultiplexed channel data; and a multiplexer activated bythe enable signal, multiplexing the channel data stored in the bufferunit and assigning the channel data to the E1 data.
 12. The apparatus ofclaim 11, wherein the channel data is a data communication channel (DCC)data and an orderwire (OW) data.